The manufacture of integrated circuits (ICs) on semiconductor wafers is a complex process and involves many different steps. Failure to correctly perform one or more of the steps on one or more wafers in a batch will likely cause the circuits on a wafer to fail. Sometimes, random circuit failures occur. Generally, there is little that can be done to avoid random failures. Moreover, random failures do not provide much information on the manufacturing process that can be used to enhance manufacturing yield.
However, failures are often distributed in a pattern as a result of one or more process steps being improperly carried out. These non-random failure patterns can serve as a guide to provide valuable information as to the sources of the failures. Thus, one of the goals of fail analysis is to get inventories of what objects on an IC actually failed along with the display, presentation, and analysis of those inventories. This information makes it possible to make a rapid identification of common failures, chip and wafer scale patterns of failures, as well as, if possible, an identification of the actual defect that caused the failures.
Fail analysis is done after manufacturing tests are performed on the IC and test data are obtained. Traditionally, fail analysis has been done only at two levels. At a first level of fail analysis, sort codes are assigned to the integrated circuits. The sort codes tell if the integrated circuit passed all the tests, or, if not, during which phase of the test the IC failed. The integrated circuits are then sorted, based on their quality, usually into two grade levels: good and reject. At the first test level, very little detail is available about what actually failed on the IC, and very little usable information is extracted from the fail data, other than the phase of the test at which the failure occurred. Consequently a second level of testing and analysis is sometimes necessary. At the second test level, detailed information is obtained, such as the generation of detailed bit maps of memory chips. These bit maps show which bits contained incorrect values at any phase of the memory test. The second level provides very detailed information, however, at the cost of an extended test session, in addition to the normal manufacturing test session, to extract the bit map data. Moreover, such a detailed analysis seems to be applicable only to memory devices.
Large volumes of wafers are manufactured every day and it is impractical to perform a detailed bit analysis of each failed object on a wafer. Therefore, in practice, only a few failed IC's are bit mapped. It is currently a manual process to choose which failing IC's to bit map by manually going through the fail data. Consequently, it is difficult to pick the failed IC's that are representative of the largest yield detractors.
U.S. Pat. No. 5,838,951 to Song describes a common method of forming a wafer map. After testing the dies or chips on the wafer, the dies are sorted into various grade levels and the positions of the dies on the wafer are recorded. The various grades of the dies on the wafer are then displayed. However, the '951 patent does not identify which objects on the dies failed or which particular device forming an object may have caused the fault.
Consequently, it is difficult to see wafer level problem areas when it is desired to select a particular failing object, such as an embedded array, to bit map. Thus, there is a need for a visual tool which gives a wafer level view of all failing objects.